1. Field of the Invention
The present invention generally relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a panel of a peripheral circuit integrated type on which a peripheral circuit and a liquid crystal display part are integrally formed on a base.
2. Description of the Related Art
A liquid crystal display panel is as small as a few inches and has relatively small delay of time due to the resistances of interconnection lines.
FIG. 1 shows a conventional liquid crystal display device, which includes a substrate 10, a data driver 12, a gate driver 14 and a liquid crystal panel 16.
The data driver 12 includes a shift register 18, display signal lines 30, a plurality of 24-bit data buses (eight sets of R, G and B lines) 22, a level shifter 24, and an analog switch unit 28. A group 26 of control signals are applied to the level shifter 24. More particularly, the control signals are a start signal DS1 and two clock signals DCLK1 and DCLK2 externally applied to the shift register 18 via the level shifter 24. In response to the start signal DS1, the shift register 18 starts to operate, and opens or close analog switches of the analog switch unit 28 by using the clock signals DCLK1 and DCLK2. Display signals R1, G1, B1, . . . , R24, G24 and B24 transferred over the 24 display signal lines 30 are applied to the liquid crystal panel 16 via the data buses 22.
The gate driver 14 is made up of a shift register 32, a buffer 34 and a level shifter 36.
The shift register 32 receives a group 40 of control signals, which are a start signal GS1, and two clock signals GCLK1 and GCLK2 externally applied to the shift register 32 via the level shifter 36. In response to the start signal GS1, the shift register 32 starts to operate, and output drive signals which serially specify data take-in positions by using the clock signals GCLK1 and GCLK2. The drive signals are then applied to the liquid crystal panel 16 via the buffer 34.
As shown in FIG. 2, the liquid crystal panel 16 is scanned from the left-hand side to the right-hand side. More particularly, the analog switches of the unit 28 connected to the leftmost 24-bit data bus 22 are closed, and the display data R1-B8 are written onto the leftmost 24-bit data bus 22. Then, the neighboring 24-bit data bus 22 is selected by closing the associated analog switches of the unit 28, and is supplied to the display data. The above operation is repeatedly carried out 100 times.
When the display data amounting to the first scanning line of the panel 16 extending from the shift register 32 has been sent thereto, the above display data is written onto the first scanning line. Thereafter, the display data is written into the 2400 data bus lines as described above, and the shift register 32 drives the second scanning line. In the above manner, the display data is written into the whole panel 16.
The display data are supplied to the 24-bit data buses 22 one by one at the different timings. This method is called dot-sequential driving method. When the number of pixels of the panel 16 is equal to 800×RGB×60 dots, the frequency of the control signals 26 is equal to 40 MHz. By dividing the frequency of 40 MHz by the number of 24-bit data buses 22, each of the 24-bit data buses 22 is assigned 5 MHz (200 ns). It is thus required to complete the writing of display data onto the 24 bus lines (24 bits equal to 8×RGB) within only 200 ns. Generally, when a compact panel has a size of a few inches and each line of the 24-bit data buses 22 is made of aluminum, the bus line has a resistance of a few kilo-ohms and a capacitance of 10 pF. If each line of the 24-bit data buses 22 has a resistance of 3 kΩ, the time constant of the bus lines is equal to 3 kΩ×10 pF=30 ns. Hence, if it is required to provide a charging time as long as five times the time constant of the bus 20 in order to settle the 24-bit data bus 22 with a sufficient margin, it is enough to write the display data onto the 24-bit data bus 22 for about 150 ns. Hence, there is no problem.
However, when the panel 16 has a large size of 10 inches or more, each line of the 24-bit data buses 22 has a resistance of 10 kΩ or more. Additionally, the resistance of the display signal lines 30 cannot be neglected. The resistance of the display signal lines 30 can be reduced if an increased number of lines 30 is used, as shown in FIG. 3. The structure shown in FIG. 3 employs 300 display signal lines to which display signals D1-D300 are respectively applied. The display signal lines 42 can be driven by a general—purpose data driver IC marketed. When a increased number of display signal lines is used, the display data can be written onto the data buses 22 for a longer time. Hence, the width of each of the display signal lines 42 can be reduced. However, the total width of the display signal lines 42 is approximately equal to 6.0 mm. This increases the size of the peripheral circuits with regard to the panel 16.
It may be possible to use an intermediate number of display signal lines (for example, 100 lines) in order to reduce the size of the peripheral circuits formed on the substrate 10. The intermediate number of display signal lines is driven by the general-purpose data driver IC. As the number of display signal line is reduced, the available write time is reduced. Hence, it is required to increase the width of each of the display signal lines. However, as the width of each of the display signal lines is increased, the cross coupling capacitance formed between each display signal line and the associated data bus line is increased. For example, if each of the display signal lines is 90 μm wide and each of the data bus lines 22 is 5 μm wide, the cross coupling capacitance is as large as 150 pF. Since the general-purpose data driver IC has a driving capability of approximately tens of pF, it cannot drive the 100 display signal lines.
It can be seen from the above that it is required to reduce the cross coupling capacitance and the area on the substrate 10 occupied by the display signal lines. Unless the above requirements are satisfied, the liquid crystal display device of a large size does not have satisfactory performance.